The present disclosure relates to integrated circuit (IC) device manufacturing processes and processing equipment.
Many years of research have been devoted to reducing the critical dimensions (CDs) and structure densities of ICs. As densities have increased, the resistance capacitance (RC) delay time has become a limiting factor in circuit performance. RC delay can be reduced by forming metal interconnect structures using copper (Cu) in place of aluminum and low-k or extremely low-k dielectrics in place of silicon dioxide.
Cu metal interconnect structures are typically formed by damascene processes. As the term is used in the present disclosure, a “damascene process” can be a dual damascene process. In a typical damascene process, a desired pattern of holes and trenches is etched into a dielectric. The holes and trenches are then filled with copper to form conductive vias and lines. Filling with copper typically includes the steps of cleaning the trenches, depositing a diffusion barrier layer, and depositing a copper seed layer. Copper barrier-seed tools adapted to perform these steps in situ are now commercially available.